Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications

This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends for neural recording applications. These techniques are employed for handling Common-Mode (CM) Differential-Mode (DM) artifacts and include techniques such as Average Template Subtraction, Channel Blanking or Blind Adaptive Stimulation Artifact Rejection (ASAR), among others. Additionally, a new technique for DM artifacts compression is proposed. It allows to compress these artifacts to the requirements of the analog frontend and, afterwards, it allows to reconstruct the whole artifact or largely suppress it.Ministerio de Economía y Empresa TEC2016-80923-

A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation

A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioral models simulations were carried out to prove the correct functionality of the proposed approach.Ministerio de Economía y Competitividad TEC2016-80923-

Sobre el uso de técnicas chopper para la reducción del ruido flicker en amplificadores para la captación de señales neuronales

La captación de señales neuronales mediante electrodos conectados a circuitos micro-electrónicos es necesaria para aplicaciones clínicas y para el control de prótesis senso-motoras, entre otras muchas aplicaciones bio-médicas. En todas estas aplicaciones, la preservación de la información contenida en las imágenes captadas depende críticamente de las prestaciones de los amplificadores empleados en la cabecera de la cadena de procesamiento electrónica. El problema es que se trata de señales muy débiles (rango de V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja V) y de baja frecuencia (rango de sub-Hz), lo que implica una enorme influencia del ruido flicker. Al margen de esta influencia, el diseño de estos amplificadores, y de las cadenas de procesamiento completas, está condicionado por restricciones severas de área y consumo de potencia. En el Instituto de Microelectrónica de Sevilla está activa una línea de investigación sobre el diseño de interfaces de señal-mixta para captación de señales neuronales. Se han concebido, prototipado en forma de chips y validado mediante medidas “in-vitro” e “in-vivo” chips con 64 canales, con calibración “on-chip” y compresión de la señal “on-chip”, con captación de energía mediante enlaces inductivos. Estos circuitos emplean amplificadores seleccionados mediante técnicas de optimización para conseguir mínimo ruido con mínimo consumo de potencia. Sin embargo, no incluyen técnicas específicas para la reducción del ruido flicker. Además, estudios posteriores han permitido vislumbrar la posibilidad de mejorar las topologías de amplificadores, en particular usando la topología denominada active-feedback time constant enhanced neural amplifier, que se presenta en el Capítulo1 de esta Memoria. Este trabajo Fin de Grado se propone con el objetivo de desarrollar modelos y técnicas para reducción del ruido flicker en amplificadores neuronales, con una doble perspectiva: Modelar dicho ruido en este tipo de amplificadores con vistas a la optimización del diseño de los mismos. Incorporar técnicas de modulación Chopper en los amplificadores neuronales y evaluar su impacto sobre las prestaciones de los amplificadores. En particular, estudiar, a nivel de modelos eléctricos, cómo afecta la aplicación de la técnica de Chopper en amplificadores del tipo active-feedback time constant enhanced neural amplifier. Explorar la posibilidad de generar ruido flicker mediante circuitos simples, adecuados para ser embebidos “on-chip” en sistemas de captación de señales neuronales, con los propósitos, no explorados en este trabajo, de auto-testado y calibración. Los modelos y técnicas propuestas nos han permitido reducir hasta 40dB la potencia del ruido en el amplificador para frecuencias inferiores a 1 Hz, lo cual nos permite constatar la validez de los resultados. De hecho, sobre la base de estos resultados, se está trabajando en la actualidad para diseñar y prototipar un chip que integra las soluciones propuestas en este trabajo. Respecto a la generación de ruido “on-chip” se han propuesto combinaciones de mapas discretos que pueden ser parametrizados para obtener densidades espectrales de potencia con distribución frecuencia propia de distintos tipos de ruido pertinentes para los objetivos del trabajo.The uptake of neural signals through electrodes attached to micro-electronic circuits is needed for clinical applications and control sensorimotor prostheses, among many other bio-medical applications. In all these applications, the preservation of the information contained in the captured images depends critically on the performance of the amplifiers used in the header of the electronic processing chain. The problem is that there are very weak (V range) and low frequency (sub - Hz range) signals, which implies a huge influence of flicker noise. Apart from this influence, the design of these amplifiers, and complete processing chain, is conditioned by severe restrictions of area and power consumption. At the Institute of Microelectronics of Seville there is an active research on the interface design- mixed signal to seize neural signals. They are designed, prototyping in the form of chips and validated using measures "in-vitro" and "in-vivo" chips with 64 channels, calibrated on-chip and signal compression on-chip with capture energy by inductive links. These circuits employ amplifiers selected by optimization techniques to achieve minimal noise with minimal power consumption. However, they do not include specific techniques to reduce the flicker noise. In addition, further studies have allowed to glimpse the possibility of improving this kind of amplifiers, particularly using the topology called active-feedback time constant neural enhanced amplifier, which is presented in Chapter 1 of this Report. This work is proposed with the aim of developing models and techniques for reducing flicker noise in neural amplifiers with a dual perspective: Modeling such noise in this type of amplifiers with the purpose of optimizing their design. Incorporate Chopper modulation techniques in neural amplifiers and assess their impact on the performance of amplifiers. In particular, to study at electric models level, how the application of the technique Chopper affects amplifiers of the active-feedback amplifier time constant neural enhanced kind. Explore the possibility to generate flicker noise by simple circuits, suitables for embedded on-chip systems for capturing neural signals, for purposes not explored in this work, as self-testing and calibration. The proposed models and techniques have allowed us to reduce up to 40dB noise power in the amplifier for less than 1 Hz frequencies, which let us verify the validity of the results. In fact, there is currently some work based on these results to design and prototype a chip that integrates the solutions proposed in this project. Regarding noise generation on-chip, it has been proposed combinations of discrete maps that can be parameterized to obtain spectral power densities with natural frequency distribution of different types of noise, relevant to the objectives of the work.Universidad de Sevilla. Grado en Ingeniería Electrónica, Robótica y Mecatrónic

A Sub-μVRms Chopper Front-End for ECoG Recording

This paper presents a low-noise, low-power fully differential chopper-modulated front-end circuit intended for ECoG signal recording. Among other features, it uses a subthreshold source-follower biquad in the forward path to reduce noise and avoid the implementation of a ripple rejection loop. The prototype was designed in 0.18μm CMOS technology with a 1V supply. Post-layout simulations were carried out showing a power consumption below 2μW and an integrated input-referred noise of 0.75μV rms , with a noise floor below 50 nV√Hz, over a bandwidth from 1 to 200Hz, for a noise efficiency factor of 2.7.Ministerio de Economía y Empresa TEC2016-80923-

A High TCMRR, Inherently Charge Balanced Bidirectional Front-End for Multichannel Closed-Loop Neuromodulation

This paper describes a multichannel bidirectional front-end for implantable closed-loop neuromodulation. Stimulation artefacts are reduced by way of a 4-channel H-bridge current source sharing stimulator front-end that minimizes residual charge drops in the electrodes via topology-inherent charge balancing. A 4-channel chopper front-end is capable of multichannel recording in the presence of artefacts as a result of its high total common-mode rejection ratio (TCMRR) that accounts for CMRR degradation due to electrode mismatch. Experimental verification of a prototype fabricated in a standard 180 nm process shows a stimulator front-end with 0.059% charge balance and 0.275 nA DC current error. The recording front-end consumes 3.24 µW, tolerates common-mode interference up to 1 Vpp and shows a TCMRR > 66 dB for 500 mVpp inputs.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research (USA) N00014111031

A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5–200 Hz band of 1.4 µVrms for a spot noise of about 85 nV / √Hz. The system draws 1.5 µW per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios

A 32 Input Multiplexed Channel Analog Front-End with Spatial Delta Encoding Technique and Differential Artifacts Compression

This paper describes a low-noise, low-power and high dynamic range analog front-end intended for sensing neural signals. In order to reduce interface area, a 32-channel multiplexer is implemented on circuit input. Furthermore, a spatial delta encoding is proposed to compress the signal range. A differential artifact compression algorithm is implemented to avoid saturation in the signal path, thus enabling reconstruct or suppressing artifacts in digital domain. The proposed design has been implemented using 0.18 μm TSMC technology. Experimental results shows a power consumption per channel of 1.0 μW, an input referred noise of 1.1 μVrms regarding the bandwidth of interest and a dynamic range of 91 dB.Ministerio de Economía y Competitividad TEC2016-80923-POffice of Naval Research ONR N00014- 19-1-215

HLA association with the susceptibility to anti-synthetase syndrome

Objective To investigate the human leukocyte antigen (HLA) association with anti-synthetase syndrome (ASSD). Methods We conducted the largest immunogenetic HLA-DRB1 and HLA-B study to date in a homogeneous cohort of 168 Caucasian patients with ASSD and 486 ethnically matched healthy controls by sequencing-based-typing. Results A statistically significant increase of HLA-DRB1*03:01 and HLA-B*08:01 alleles in patients with ASSD compared to healthy controls was disclosed (26.2% versus 12.2%, P = 1.56E?09, odds ratio?OR [95% confidence interval?CI] = 2.54 [1.84?3.50] and 21.4% versus 5.5%, P = 18.95E?18, OR [95% CI] = 4.73 [3.18?7.05]; respectively). Additionally, HLA-DRB1*07:01 allele was significantly decreased in patients with ASSD compared to controls (9.2% versus 17.5%, P = 0.0003, OR [95% CI] = 0.48 [0.31?0.72]). Moreover, a statistically significant increase of HLA-DRB1*03:01 allele in anti-Jo-1 positive compared to anti-Jo-1 negative patients with ASSD was observed (31.8% versus 15.5%, P = 0.001, OR [95% CI] = 2.54 [1.39?4.81]). Similar findings were observed when HLA carrier frequencies were assessed. The HLA-DRB1*03:01 association with anti-Jo-1 was unrelated to smoking history. No HLA differences in patients with ASSD stratified according to the presence/absence of the most representative non-anti-Jo-1 anti-synthetase autoantibodies (anti-PL-12 and anti-PL-7), arthritis, myositis or interstitial lung disease were observed. Conclusions Our results support the association of the HLA complex with the susceptibility to ASS

Role of the IL33 and IL1RL1 pathway in the pathogenesis of Immunoglobulin A vasculitis

Cytokines signalling pathway genes are crucial factors of the genetic network underlying the pathogenesis of Immunoglobulin-A vasculitis (IgAV), an inflammatory vascular condition. An influence of the interleukin (IL)33- IL1 receptor like (IL1RL)1 signalling pathway on the increased risk of several immune-mediated diseases has been described. Accordingly, we assessed whether the IL33-IL1RL1 pathway represents a novel genetic risk factor for IgAV. Three tag polymorphisms within IL33 (rs3939286, rs7025417 and rs7044343) and three within IL1RL1 (rs2310173, rs13015714 and rs2058660), that also were previously associated with several inflammatory diseases, were genotyped in 380 Caucasian IgAV patients and 845 matched healthy controls. No genotypes or alleles differences were observed between IgAV patients and controls when IL33 and IL1RL1 variants were analysed independently. Likewise, no statistically significant differences were found in IL33 or IL1RL1 genotype and allele frequencies when IgAV patients were stratified according to the age at disease onset or to the presence/absence of gastrointestinal (GI) or renal manifestations. Similar results were disclosed when IL33 and IL1RL1 haplotypes were compared between IgAV patients and controls and between IgAV patients stratified according to the clinical characteristics mentioned above. Our results suggest that the IL33-IL1RL1 signalling pathway does not contribute to the genetic network underlying IgAV.Acknowledgements: We are indebted to the patients and healthy controls for their essential collaboration to this study. We also thank the National DNA Bank Repository (Salamanca) for supplying part of the control samples. This study was supported by European Union FEDER funds and `Fondo de Investigaciones Sanitarias´ (Grant PI18/00042) from ‘Instituto de Salud Carlos III’ (ISCIII, Health Ministry, Spain). DP-P is a recipient of a Río Hortega programme fellowship from the ISCIII, co-funded by the European Social Fund (ESF, `Investing in your future´) (Grant Number CM20/00006). SR-M is supported by funds of the RETICS Program (RD16/0012/0009) (ISCIII, cofunded by the European Regional Development Fund (ERDF)). VP-C is supported by a pre-doctoral grant from IDIVAL (PREVAL 18/01). BA-M is a recipient of a `López Albo´ Post-Residency Programme funded by Servicio Cántabro de Salud. LL-G is supported by funds from IDIVAL (INNVAL20/06). OG is staff personnel of Xunta de Galicia (Servizo Galego de Saude (SERGAS)) through a research-staff stabilization contract (ISCIII/SERGAS) and his work is funded by ISCIII and the European Union FEDER fund (Grant Numbers RD16/0012/0014 (RIER) and PI17/00409). He is beneficiary of project funds from the Research Executive Agency (REA) of the European Union in the framework of MSCA-RISE Action of the H2020 Programme, project 734899—Olive-Net. RL-M is a recipient of a Miguel Servet type I programme fellowship from the ISCIII, co-funded by ESF (`Investing in your future´) (Grant Number CP16/00033)

Cultura urbana en televisión. Programa cultural realizado por profesores y alumnos de la Facultad de Ciencias de la Información

Con un enfoque para la docencia que plantea una universidad basada en el entusiasmo y en la participación a través de un modelo de aprendizaje que motive y sepa entusiasmar a los estudiantes, planteamos como proyecto de innovación para mejora de la calidad docente la creación de un programa de televisión sobre la cultura urbana vinculado a las asignaturas de: - "Producción y realización publicitaria" (Grado en Publicidad y Relaciones Públicas) - "Realización publicitaria" (Grado en Comunicación Audiovisual) - "Dirección cinematográfica" (Grado en Comunicación Audiovisual) - "Realización televisiva" (Grado en Comunicación Audiovisual) Y a los TFG relacionados con las áreas de conocimiento de realización y producción.Se crearían tres categorías en las que los alumnos podrían participar con sus trabajos: rodajes,reportajes audiovisuales y reportajes fotográficos y spots publicitarios. Los alumnos, tras haber pasado por alguna de las asignaturas o TFG propuestos, con sus respectivas prácticas, ya tienen un training que les capacita para sacar adelante un trabajo colaborativo, un proyecto y además les forma en las competencias profesionales necesarias para el trabajo en equipo. Además, el proyecto incluye la creación de una web y un laboratorio audiovisual (que ya está en marcha) para la difusión de los trabajos presentados y como herramienta para ampliar la proyección profesional y académica de los alumnos. El reto es poner Internet al servicio de la capacidad creativa y técnica de los estudiantes como fórmula para descubrir el nuevo talento, para poder experimentar con un nuevo medio al alcance de todos, y para conseguir una muy amplia difusión. Internet, lo interactivo, lo virtual y lo on-line serían las grandes herramientas para la realización de este proyecto. Es una experiencia de trabajo en el que varias asignaturas se unen y en el que la planificación y la nota final de cada una de las asignaturas se consolidan un proyecto real para dar a conocer el funcionamiento del mundo laboral. Es un proyecto de integración de varias asignaturas que suman un conjunto de experiencias en los que la innovación es la primera premisa